Rambus (RMBS): Trial notes 3/21/06 From calbiker w...

Reply Private New

Next 10 Prev Next

Send PM Follow Ignore

Followers	9
Posts	4835
Boards Moderated	0
Alias Born	09/30/2000

Threejack

Re: None

Wednesday, 03/22/2006 8:47:51 AM

Wednesday, March 22, 2006 8:47:51 AM

Trial notes 3/21/06

From calbiker with his correction

============================

There was plenty of excitement today. At least for cal. wink

Furniss conducted the cross on Murphy. I thought Rambus would have problems with the CAS latency register and DLL due to Whyte’s previous restrictions; but it didn’t happen. Murphy and Furniss were battling it out for several hours. In my view, Murphy won each battle. There was only one instance where Furniss slightly cut into Murphy when asked if Murphy owned any patents outright. Murphy didn’t. That puestion was asked at the very end, when Furniss wanted at least one ‘winner‘.

I believe Furniss went through all 14 elements that were covered the past 2 days. He down played most of the elements (and he’s correct). Stating the elements are common, long before the patents were originated. He has objections to a few elements:

1. Read with precharge
2. DLL
3. Output driver coupled to external clock
4. Access time register (CAS latency register)

Note, there may also be objections to dual edge clocking and block size. They were not discussed today.

1. Read with precharge.

Furniss wanted the jury to believe this can be two separate commands. Murphy: No, the claim is one integrated command. Murphy made it clear that providing a read cmd and then a precharge cmd will result in a different operation mode. In the integrated case, the read burst can not be terminated if desired. In the two command case, burst read can be terminated.

2. DLL

Furniss: just because DLL is written all over the schematics doesn’t mean it’s really DLL. You gotta love that comment. Ha. But Murphy agreed. This was another long discussion. Furniss maintained Hynix didn’t use a DLL. Murphy states all you need is an input, an output and a variable delay line. Hynix’s schematics show all elements of a DLL. F: Hynix uses fixed delay lines. M: There are different ways to slow down a signal; either speed or distance. It doesn’t matter which method you use. There are many ways to delay a signal. F: Each circuit (delay element) is not a variable delay line. M: But the upper schematic has control signals which determines which path is taken.

Murphy clearly showed (at least to cal) that Hynix uses a DLL.

3. Output driver coupled to external clock

Furniss maintains the output driver is not coupled to external clock. Note, this is synchronous memory operation. Furniss says the output driver signal is just a pulse, not a periodic clock. (The guy is really desperate and grasping at straws.) After a long discussion Murphy comes up with the court given definition of a internal clock signal. The signal are GATED. That means the signal doesn’t have to be a periodic clock. It can be a single pulse that has same rising edge as the external clock (which it is).

4. CAS latency register

Furniss was really adamant that the number placed in the latency register does not coincide with the number of clock cycles delayed before data is sent (as stated in the patent claim). This discussion was a real battle and Murphy kept his cool through out. It was surprising though, how much DRAM knowledge these lawyers obtained.

The problem was that Furniss was just splitting hairs. He tried to make it appear the claim was different than Hynix’s DRAM, but it wasn’t. The real issue is, there’s a finite amount of time when the DRAM outputs the data, to when the data is read by the memory controller. The CAS time is referenced to the memory controller. Furniss was referencing the output DRAM driver. Furniss' point of reference is really not important, trying to inject FUD.

JJ Lee, the last witness who is a Hynix DRAM EE verified Murphy’s position.

Don’t know how much the jury got out of this, but cal found it quite interesting. Ha.

Yo Nic-

Looks like Teece is up tomorrow.