Trial NoteS 4/10/06 Part 1
Murphy was back on the stand all afternoon. Same combo Medlock and Furness questioning Murphy.
Hynix must have discussed prior art last week.. Medlock spent lots of time having Murphy explain the prior art cited by Hynix: (not sure of spellings) Redwine, Johnson article, TI Novac patent, Locren Patent, Haider reference, Buddy patent, IAPX432, SCIA & SCIC articles, Chapel, CVAX. That’s all I recall, but could be more. Murphy when into detail why each reference is different from the Rambus claims. For example, Redwine uses sensed signals, not sampled data (as R. uses). Or that the Locren Patent used external RC or LC delay lines, not DLL. Or Chapel uses a hard wired precharge after every cycle, not programmable precharge with read. The list goes on….
Then Murphy went through all R. patents in question and again explains why the listed prior art does not negate R. claims. It was a long process.
Murphy spoke shortly about secondary considerations. He did use then. I believe the 2 main ones cited are the growing speed gap between memory and the cpu, and acceptance. He again stated none of the claims are anticipated or obvious.
Next Murphy addresses the issue that many claims are not in the original patent (R. generated new claims later reading against SDRAM & DDR).
1. Access Time Register. Murphy shows the ATR was mentioned in the original patent application, not in the claims, but the invention description.
2. Dual Edge Clocking. Murphy shows that a patent discusses a 250MHz clock with data output at 500MHz. Even though DEC is not mentioned, data is output on both the rising and falling edge of the 250MHz clock. My note, It’s a matter of connecting the dots (for a person skilled in the art).
3. DLL. The ‘898 application, Fig. 12 shows a delay line and feedback circuitry. There’s also text mentioning variable delay line with feedback. DLL however is not mentioned. But it’s very obvious for a person skilled in the art.
4. Operation code. Some text is cited.
5. Block Size. ‘916 patent cited.
6. Bus. Here the emphasis was that it doesn’t have to be a narrow bus. Several examples were shown that the patent states ‘16 bus data lines or other number of data lines can be used’, or another location: ‘any size bus can be used’.
Murphy then discusses bus size vs. bandwidth. We’ve done enough of that here. Ha. Anyways, I hope we all know this now, bus size is proportional to BW. Double data bus, double BW. But a larger bus gets more expensive.
That’s it for now. Less than half done. Don’t know when the rest comes. It‘s Miller time. Ha.
Looks line we’ll be done Thursday. They wanted to go all day Wednesday, but one jurist nixed it. There was one young lady who amazed Cal. She actually took lots of technical notes. HA.
