Trial Notes 4/10/06 Part 2
Murphy next discussed the components that Hynix says are not contained in their devices:
1. Read Request. We see again the 3 read timing diagrams. A couple of weeks ago Furness asked Murphy if he knew the differences between the diagrams. As I recall he couldn’t tell any differences. So now Murphy gets back to these diagrams. It turns out Hynix had deleted important information from the diagrams. Among other things, in the read burst with precharge, The warning ‘Illegal to terminate burst’ was deleted. It’s clearly shown in Hynix’s datasheet.
2. Access Time Register. Murphy goes over same material as last time. If the latency is 2, then the delay is 1 clock cycle plus a time t. If latency is 3, delay is 2 clock cycles plus a time t.
3. Output data on rise and fall edge of clock. The cross over points determine when data is ready to be transmitted.
4. DLL. Murphy goes over Hynix block diagram. He shows the DLL block goes to the output buffer. Output driver is coupled to DLL block.
Furniss takes over. Don’t know what he’s trying to achieve on many of these issues other than confuse the jury.
He starts off with Read with Autoprecharge. He asks Murphy if the precharge erases the data. Murphy says yes. Furniss then asks if it’s not odd the data is being erased when the object is to read? This is really wacko! As I understand it, the sense lines are precharged to a defined voltage level before the memory cell is read. Murphy didn’t make this very clear. No data is erased. Anyways, it has nothing to do with this case. He’s just injecting FUD.
2. Access Time Register. Furniss thinks it’s strange that the delay is a certain number of clock cycles plus an additional time t. Murphy replies that’s what the concept of representative implies. In other words, the CAS latency value is representative of a delay. Murphy again says the CAS latency is important to the system builder. To receive the data in 2 cycles, the data must be sent before the second cycle ends.
There was a small discussion regarding Taylor’s contention that the pipeline architecture is what makes the DRAM go fast. Murphy wasn’t that convinced. Large pipelines can also make the DRAM go slower.
3. Rising and Falling edge clock was briefly discussed. M: Can’t have crossing point without rising and falling edges.
4. DLL. Furniss maintains there’s a pulse that initiates the output drivers. M: The pulse is generated by the DLL. The clock is coupled to the output drivers. That’s what the diagram shows (this is of course a Hynix datasheet diagram).
Again, Furniss maintains their circuit contains fixed delay lines. M: Voltage control is not the only way to create a delay line.
It appears to me that Murphy’s argument is rather weak. He could get into much more detail. He never explains by connecting many fixed delay lines together one gets a variable delay line. Is this due to Whyte’s limitation on DLL? No equivalence is allowed? All Murphy says is that there’s a line in a line out and it has delay. Seems like he could do a lot more.
Part 3 to follow tomorrow.
