Rambus (RMBS): Trial Notes 4/11/06 Furness continues...

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calbiker

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Tuesday, 04/11/2006 7:42:39 PM

Tuesday, April 11, 2006 7:42:39 PM

Trial Notes 4/11/06

Furness continues to cross Murphy.

F: Operation Code- where is it included in the patent?
M: In the preferred embodiment.
F: Hynix doesn’t use block size in packet format.

F: How many claims limited to DRAM?
M: One,’120 claim 33
F: Yes, 2 claims are IC related, and the rest are synchronous memory related.

F: Why doesn’t Redwine relate?
M: It doesn’t describe DRAM. There’s no random access.
F: Does it have double data rate?
M: Yes
F: Shows part of the Redwine circuit composed of a delay circuit. He wants us to believe it’s a clock alignment circuit.
M: It’s not clock alignment because there’s no adjustment capability. The circuit just delays and does wave shaping.
F: But it meets the courts definition.
M: In my opinion, it doesn’t.

F: Buddy reference (memory controller with on-chip FIFO) - Murphy testified it’s not a synchronous memory device. Buddy contains a request FIFO which is used for temporary storage. Is FIFO a memory device?
M: As used here; NO. Look at definition: A device where info can be stored and retrieved. In Buddy you can not retrieve data from the FIFO. When you request the data, data comes from the main memory. Court requires data to be stored and retrieved. It can’t be retrieved from FIFO.
F: All right. I think I understand it. [Well finally. LOL]

Next Furness discusses the idea of moving memory controller functions to the DRAM device. Just like some Rambus inventions, but done earlier.
F: CVAX reference: The Intel memo describes moving all controller functions on the IRAM device.
M: Statement is not correct. ECC is not included. Mostly see refresh function.
F: Look at the diagram, there’s many functions being moved.
M: The diagram shows arrays, they are always on the memory device, then address latch, also always on. What’s left is refresh.

F: Lofgren UK patent application- it describes a DLL (as defined by court). They suggest adding DLL to DRAM.
M: The DLL would be external to the DRAM.
F: Where is that stated?
M: Doc. Doesn’t tell us. At that time, timing was done external to DRAM.
F: It doesn’t say it’s external.
M: The RAS & CAS signals are not periodic. It’s not possible to lock onto a signal if it’s not periodic. Timing control is done external to the DRAM at that time.
F: Were there delay lines on DRAM at that time?
M: Yes. Any signal can be delayed inside a DRAM, but not delay locked loop.

F: Novac, per Murphy does not disclose block size info. Basis?
M: The phi clock cycles determines # of data output. Not an opcode. Def: Info that specifies total amount of data to output. Novac doesn’t specify an amount of data.

F: Was IRAM cited at PTO?
M: Don’t know.
F: It was not cited. Can things get combined from different circuits/functions?
M: If you know what you’re doing. The conventional DRAM at that time did not have a periodic signal. A DLL can’t lock.

F: You used secondary considerations for obvious. Gap in speed. Do you have evidence that inventions increased speed in DRAM?
M: DRAM speed has increased. The bandwidth goes up when these features are used.
F: Hasn’t the performance gap gotten worse?
M: The gap would be even larger without the features.
F: Gets Computer Architecture book and shows processor performance and DRAM speed graph over time period 1980 to 2005. The chart reflects no dramatic increase in DRAM speed (after implementing the inventions).
M: Have to check text in book.
F: The rate in DRAM speed remains constant. No boost from R. inventions.
M: This chart is relative to processor speed. Can’t tell what DRAM does.

That was about it for Murphy…. For the moment. He later applies his law when power is shutdown. wink

Stone then reads an excerpt of a deposition from Sung Bun Kil. A Korean applications engineer. Guess it went by so fast that Cal didn’t catch the meaning.

Mark Horowitz was next, the main event of the trial. He was worth the price of admission.

Stone questioned him on how Mark and Mike met (at MIPS) and how they got together to solve the memory gap. They were Mike’s ideas, and Mark figured out how to make it work. Mark did IC design and chip implementation.

He defines the performance gap as the ratio of the rate at which cpu can process data to the rate at which memory can deliver data.

Stone pulls out the book ‘Computer Architecture’ (I believe it’s an earlier version of what Hynix was using before). We see a memory gap graph, showing cpu performance and memory performance. CPU performance measured in instructions/s, and memory performance in DRAM access time (latency).

Horowitz explains there’s two parts to mem performance: latency and bandwidth. Their inventions improved bandwidth, not latency. Today, there’s no bandwidth gap. From a latency perspective, we still have a gap. We now find out the chart Hynix showed displayed DRAM latency. That’s why no significant performance boost was seen after the R. inventions were used. [Those slimy lawyers will try to get away with anything. The chart Hynix showed did not look good for Rambus. Now we know.]

H: If bandwidth is charted (and not latency) then we should see 1,000x improvement.

Horowitz lists the inventions. Their goal was to improve bandwidth.
1. Low swing signals and terminated lines
2. Dual edge clocking - gets twice the data
3. Access time reg. on DRAM
4. Block Mode transfers. Get high efficiency of wires.
5. Bus arbitration
6. Device packaging.

Mark explains DRAM at that time were very simple. To keep cost down. It was Mike’s idea to add to the cost of the DRAM (add new features) so that the bus size gets smaller (and cheaper).

S: Have these inventions made improvements to DRAM?
H: In 1990 DRAM were operating at 1MB/s. Rambus made a DRAM operating at 500MB/s. A 500x improvement.

S: Did you share the idea with others?
H: Yes. Talked to system companies (Intel, IBM, Sun) and DRAM companies (TI, IBM, Toshiba, etc). They talked to Gordon Moor (Intel) who was encouraging and provided contacts to Intel. There were also negative comments: too expensive, couldn’t make DRAM go that fast. In early 90’s did test chip with Intel. Used dual edge clock, low signaling, terminations. In 1992 Toshiba built a 4Mb Rambus DRAM operating at 500 Mb/s.

Last (before Murphy had the last word), Stone discussed the IEEE award H. just got. Part of the reason for the award was due to the work he did with Mike on DRAM memory. That left a huge impression. Especially when Furness just got through explaining R. inventions did nothing for the DRAM industry. LOL