Trial Notes 4/13/06 Part 4 Do NOT re-post without permission!
For mature audiences only. HA.
Furniss
Issue: Do claims read on H parts? Case is not about F & H inventions. It’s about claims.
What’s the breath of inventions? Claims were generated much later.
H manufactures JEDEC based DRAM parts. H has to build products that comply to JEDEC standard.
Rambus is a tech company. Very successful. They have been rewarded for their inventions.
Validity – H has heavy burden. But the evidence is there.
Patents describes a ramBUS.
H parts use Probstein invention, not R inventions.
The invention is a new form of bus. Don’t even need memory. H doesn’t produce a bus it produces memory devices. Our architecture just isn’t there.
Protocol- Stone says H uses R protocol. Looking a press package (from ’92), R solution is 10x improvement … on a narrow high speed bus. Didn’t hear dual edge clocking. You hear of a narrow high speed bus. They had a revolutionary high speed bus.
Probstein worked for H.
April 1990 Patent application. March ’92 announce inventions.
Oct ’97 R hires Karp (was with Samsung).
hired to license non-complementary parts
need claims that read on products
already had 8 issued patents
Karp was disappointed with R patents
Why? Didn’t see claims covering ‘actual’ inventions
Worked with N. Steinberg in 1998 to create the Strategic Patent Portfolio (I believe that was a sales pitch to get the R job).
Steinberg says R hasn’t claimed all inventions.
R Strategy Update: Replace Sokoloff (original patent attorney) with Steinberg. Aggressively claim precharge, DLL, block size, dual edge clocking, etc. File them in various combinations and permutations. An explosion of patent filings followed. Want more money? Write more claims. Steinberg wrote claims on own authority. He filed over 100 claims, but didn’t talk to F & H. Steinberg is not skilled in the art, but filed claims anyways.
Some people patent inventions. Some people invent patents. That’s what Steinberg did.
These 10 claims are not what F & H invented. Claims are just pieces of invention. Anything that’s mentioned in the patent is written as a claim.
R. Main inventions:
1. Dual edge clocking – Term never appears in patent. TI invented dual edge clocking in 1980.
2. DLL – It’s just a piece of Fig. 12. No early & late clock in H Parts. If you had a fundamental invention worth $100’s of millions, would you only put it in a figure? See little in patents, none on DLL, but lots of bus.
3. Block Size – Is mentioned in context of a narrow multiplexed bus and packets. BS has been know long before. It’s only unique to this architecture.
4. Access Time Reg – H doesn’t use that architecture. [Say what?] H uses pipeline architecture. Latency has different function. Not waiting, but being available when you want it. Lee- states when the data must be available. [Hopefully the jury has a clue. He’s trying to create confusion.]
Prior Art:
Anticipated – it’s not new.
Obvious – look at scope and content of Patent Application
Furniss goes through PA:
Redwine reference: ’82 TI patent. Concept of Double data rate. Murphy says it isn’t DRAM, refers to RAS & CAS. Not true.
Novak: TI patent – Dual edge clock.
SCI (Scalable Coherent Interface): In 1988 they were contemplating using double data rate. Both edges active. Concept of DDR was already out there.
References in front of PO are only preliminary. Over 100 references in patents. People make mistakes. When patent gets sued upon, it’s put to the jury.
Lofgren 1988 – Discloses DLL to control DRAM. Murphy states the DLL is external to DRAM. But the external reference is not present in the patent.
Johnson: Shows a voltage controlled variable delay line. Didn’t catch rest.
Budde: iAPX is product. Has programmable access time register.
CVAX: Discloses access time reg.
Motivation to combine: IRAM reference – integrate controller circuits and put them on memory. Murphy: only includes refresh. That’s not credible.
Block Size – Novac, SCI, AIPX
Precharge- existed since DRAM. Chappel patent
Two experts:
Taylor has 40 years history. > 20 patents. Mostek Corp.
Murphy: never designed DRAM. Provided us with “3 = 2” testimony. When CAS = 2: 2 = 1 doesn’t make sense.
Infringement:
CAS latency- not a matter of waiting, but being there. They are different functions.
Read Request: R states there are 2 types of read. …
Coupled to: - Provides example of speech. You hear me, but is your ear coupled to my tongue? I don’t think so. [Furniss provides another bad example. His mouth is coupled to juries ears by way of sound waves. More fud]
H parts outputs data in response to pulses. Data is not output to rising and falling edges. [More semantics, it’s the crossing point of rising and falling edge.]
DLL- Issue is variable delay line. H has fixed delay elements. [True, but delay elements are configures as a variable tap. Stone is weak in putting down Furniss argument.] Person skilled in the art understands DLL as a variable voltage control delay line. [Bull Shit]
Damages:
The hypothetical negations assume 3.5%. Stone now is looking for a multiple of 3.5%?
TI has 12,000 patents. They get royalties from H. Would you pay the same amount to a company who has 6 patents?
H survival was at question. Those who listened R had financial disaster. Delay doesn’t help.
Remember R wanted non-negotiable 3.5%.
Performance gap:
The credibility of R at stake. For 5 weeks they stated they solved the performance gap. Now the evidence shows it’s just not true. Hennecy Chart – It’s linear. The performance gap got wider. Where on the line did the revolution occur? There’s no dramatic increase from 1980 to present.
Rambus employee Woo shows processor – memory gap widening. How can they say they solved the performance gap? It’s a marketing slogan!
Stone is next, with some of his best stuff. Perhaps tomorrow. Happy Easter.
