Advanced Micro Devices Inc (AMD): OK, let's do some calc and refine my gue...

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DDB

Re: wbmw post# 12072

Wednesday, 08/27/2003 6:34:21 AM

Wednesday, August 27, 2003 6:34:21 AM

OK, let's do some calc and refine my guesses.

Some time ago I analyzed the sizes of several parts of the Opteron die. Source: http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_572_573%5E5766~69715,00.html

33.6% AMD64 Core
24.8% HT/mem controller
41.6% L2 cache

If you compare Intel's and AMD's cache sizes you see the advantage which Intel has with it's 2.09µm^2 and 1µm^2 SRAM cells in 130nm and 90nm. IBM has a 2.16µm^2 SRAM cell in 130nm. Somewhere I read (should have the link still bookmarked) AMD had to use bigger SRAM cells for SOI than for their bulk process because of some design problems.

Now let's shrink (and BTW the wafer I saw looked more like a 100nm process than 90nm..):

Estimated 121mm^2 size of simply shrinked core.
40.6 mm^2 Core
30 mm^2 controller
50.3 mm^2 L2 cache (1MB)

Now a standard core + 256kB L2 + 1Mem and 1HT controller (they need about 40% of the whole controller area) will take around 40.6+12+12.6 mm^2, summing up to 65.2mm^2. IBM's SRAM cells would roughly half the cache area, pushing us to below 60mm^2 in a ~100nm process. And that's no shrinking, buz cutting off unnecessary parts.

That is no wishful thinking, just an educated guess. And consider that for a real 130nm->90nm shrink the die size should be about 50% after shrinking. But it's still not. Maybe now AMD comes closer than earlier in the year. I have no information at which time this wafer was produced.

DDB